Power amplifier with bias control

ABSTRACT

A power amplifier ( 100 ) suitable for use in mobile telecommunications equipment has a first stage ( 2 ) and an optional second stage ( 2 ), each stage being provided with a bias circuit ( 4, 5 ). To provide a well-defined gain characteristic, in the first stage ( 1 ) a bias current (Ib 1 ) is fed into a signal amplifying transistor (T 1 ). The first bias circuit ( 4 ) comprises non-linear a voltage/current converter ( 41 ) coupled to a current mirror ( 40 ). To suit alternative applications, such as GSM and UMTS requiring a different bias, plural voltage/current converters ( 41, 42 ) may be provided in parallel.

The present invention relates to a power amplifier. More in particular,the present invention relates to a power amplifier which may for examplebe utilized in high-frequency applications, such as mobiletelecommunications equipment.

Power amplifiers are well known. To achieve a suitable amplification ofan input signal at the various stages the amplifier may have, a gaincontrol signal typically determines the operating point and thereby thegain of each stage. To achieve a desired overall gain characteristic,the so-called power control curve, a careful tuning of the operatingpoints of the various stages is required.

An multi-stage radio frequency power amplifier is disclosed in U.S. Pat.No. 6,259,901. The first and second stages of this known multi-stagepower amplifier are differential amplifiers, each coupled to ground viaa bipolar transistor acting as a current source and to which a biascurrent is fed. The bias currents of the respective stages are suppliedby bias circuits which receive a gain control signal and a singlereference voltage. Details of the bias current circuits are notdisclosed.

This known power amplifier presupposes a balanced input signal, forwhich a differential amplifier is provided. However, in manyapplications a balanced input signal is not available or not desirable.In addition, for many applications it is necessary to have awell-defined, substantially straight power control curve. Such a powercontrol curve is not guaranteed by the power amplifier known from theabove US patent.

It is an object of the present invention to overcome these and otherproblems of the Prior Art and to provide a power amplifier forsingle-sided (unbalanced) input signals which has a well-defined powercontrol curve.

It is another object of the present invention to provide a poweramplifier the gain of which is independent of the signal to beamplified.

It is a further object of the present invention to provide a poweramplifier which is suitable for radio frequency applications.

Accordingly, the present invention provides a power amplifiercomprising:

-   a first stage for amplifying an input signal, and-   a first bias circuit for providing a bias current to the first    stage,-   the first bias circuit comprising a controlled current source, and    the first bias circuit being arranged for feeding its bias current    to a control electrode of a signal amplification transistor of the    first stage.

By feeding the bias current to a signal amplification transistor of thefirst stage, the operating point of the transistor and hence its gaincan be carefully controlled. The control electrode preferably is thebase of a bipolar transistor. The first stage preferably only has asingle transistor but if it is provided with two or more transistors,the bias current is preferably fed to the first transistor in the signalpath but may be fed to the other transistors as well.

In a preferred embodiment, a bias circuit comprises a non-linearvoltage/current converter, preferably coupled with a current mirror.That is, the relationship between the gain control signal and the biascurrent is preferably non-linear. In this way, a very advantageous gaincharacteristic can be obtained. However, approximately linearvoltage/current converters can also be utilized.

The non-linear voltage/current converter preferably comprises at leastone differential stage, each stage coupled to a reference voltage. Thedifferential amplifier may consist of only two transistors and aresistor, thus providing a very compact yet efficient circuit. Anynon-linear characteristics of the voltage/current converter can beachieved by utilizing the non-linear properties of the transistors. Iftwo differential stages are used within a single converter, each stageis preferably coupled to a distinct respective reference voltage.

In a preferred embodiment of the power amplifier of the presentinvention, at least one bias circuit comprises at least two distinctvoltage/current converters for converting two distinct gain controlvoltages. This allows a different bias to be provided for differentmodes of operation, such as, in the case of mobile telephone sets, GSM,Edge and UMTS. Each of the at least two converters may convert therespective gain control voltage into a current, as described above. In aparticularly advantageous embodiment of the present invention, however,the first bias circuit further comprises bias voltage means foradditionally providing a bias voltage to the first stage. That is, thefirst bias circuit may produce a bias current in response to a firstgain control signal and a bias voltage in response to a second gaincontrol signal. In this way, the power amplifier of the presentinvention can be easily adapted to various different applications havingdistinct requirements.

In a further advantageous embodiment, in the first bias circuit anadditional transistor is coupled between the at least onevoltage/current converter and the controlled current source so as tocompensate for the DC current gain of the signal amplificationtransistor.

To achieve a higher overall gain the power amplifier of the presentinvention may further comprise a second stage for amplifying a signaloutput by the first stage and a second bias circuit for providing a biascurrent to the second stage, and optionally a third stage for amplifyinga signal output by the second stage, and an associated third biascircuit for providing a bias current to the third stage.

The power amplifier according to the present invention may be arrangedfor amplifying high frequency signals, such as signals used for mobiletelephony.

The present invention further provides a device provided with a poweramplifier as defined above. The device preferably is a mobiletelecommunications device, more preferably a GSM telephone set.

The present invention will further be explained below with reference toexemplary embodiments illustrated in the accompanying drawings, inwhich:

FIG. 1 schematically shows a preferred embodiment of a power amplifieraccording to the present invention.

FIG. 2 schematically shows a first alternative embodiment of a firststage of a power amplifier according to the present invention.

FIG. 3 schematically shows a second alternative embodiment of a firststage of a power amplifier according to the present invention.

FIG. 4 schematically shows a non-linear voltage/current convertercircuit for use in a power amplifier according to the present invention.

FIG. 5 schematically shows an alternative embodiment of a non-linearvoltage/current converter circuit for use in a power amplifier accordingto the present invention.

FIG. 6 schematically shows the voltage/current characteristic of theconverter circuit of FIG. 5.

The power amplifier 100 shown merely by way of non-limiting example inFIG. 1 comprises a first stage 1, a second stage 2 and a third stage 3.Each stage has an associated bias circuit 4, 5, 6. The embodiment shownis designed for RF (radio frequency) applications and contains variouscomponents, in particular inductors, especially for this purpose. Theinvention is, however, not limited to RF applications and those skilledin the art will appreciate that such dedicated components may be omittedin other applications.

In the embodiment shown, the first stage 1 comprises a first bipolartransistor T₁ of the NPN-type. The input signal V_(in), in the presentexample an RF signal, is fed via a coupling capacitor C₁ to the base oftransistor T₁. The emitter of transistor T₁ is connected to ground,while its collector is connected via an inductor L₂ to a positive supplyvoltage V_(s) and via a further coupling capacitor C₂ to the secondstage 2. The first stage 1 further comprises a filter circuit consistingof a first inductor L₁, a first resistance R₁ connected in parallel toL₁, and a capacitor C₅. As this filter circuit is designed fordecoupling RF signals, its components are not essential to the presentinvention.

A first bias circuit 4 is connected to the base of the first transistorT₁ to supply a (first) bias current I_(b1). In the embodiment shown inFIG. 1, the first bias circuit 4 comprises a controlled current mirror40, constituted by transistors T₆ and T₇, and two voltage/currentconverters 41 and 42. These converters 41, 42 may receive a gain controlsignal V_(c1), V_(c2) respectively. Depending on the particular mode ofoperation of the power amplifier 100, for example GSM or UMTS, eitherthe first gain control signal V_(c1) or the second gain control signalV_(c2) is present. The converter 41 or 42 converts its respective gaincontrol signal into a current which is fed from transistor T₆ of currentmirror 40. As a result, a current I_(b1) having a proportional magnitudeis fed from transistor T₇ to transistor T₁. This bias current I_(b1),which typically is a DC current, will not be affected by inductor L₁ andwill flow effectively directly into the base of transistor T₁. As willbe clear from the above, the bias current I_(b1) is completelyindependent from the RF input signal V_(in). As a result, the operatingpoint and gain of the signal amplifying transistor T₁ are independentfrom the input signal.

In Prior Art arrangements a bias voltage is applied to the first signalamplifying transistor of the first stage. The present inventors havefound that a bias current instead of a bias voltage offers a much betterdefined operating point of the first stage of the amplifier.

The bias circuits 4, 5 and 6 of the present invention are particularlysuitable for providing a well-defined bias current. The converters 41and 42 and their counterparts 51, 52 and 61, 62 will be discussed laterin more detail with reference to FIG. 4. It is noted that in each biascircuit 4, 5, and 6 a single converter (41 or 42 in the case of biascircuit 4) would in principle suffice. According to further aspect ofthe present invention, however, multiple converters are provided perbias circuit so as to allow multiple gain control signals to be usedindependently.

The second stage 5 differs from the first stage 1 in that it comprises acurrent mirror consisting of the transistors T₂ and T₃, the bases ofwhich are coupled by an inductor L₃. The RF signal amplified by thefirst stage 1 is fed, via coupling capacitor C₂, to the base of thethird transistor T₃. Like transistor T₁, the collector of transistor T₃is connected via an inductor L₄ to a positive supply voltage V_(s) andvia a further coupling capacitor C₃ to the third stage 3. The collectorof transistor T₂ is coupled to second bias circuit 5 which is, in theembodiment shown, identical to the first bias circuit 4 and the thirdbias circuit 6. As in the first bias circuit 4, a first bias transistorT₈ and a second bias transistor T₉ form a current mirror 50, transistorT₈ being connected to converters 51 and 52 which convert gain controlvoltage signals into suitable currents. In contrast to the first stage,the collector of second bias transistor T₉ is not directly connected tosignal amplifying transistor T₃ but to the collector of transistor T₂,which together with transistor T₃ constitutes a current mirror. Atransistor T₁₂, the collector of which is connected to a supply voltageV_(s), provides a suitable base current for transistors T₂ and T₃ (basecurrent compensation). As a result, the bias of the signal amplifyingtransistor T₃ in the second stage 2 is a voltage bias rather than acurrent bias as in the first stage 1. A current bias would be possiblein this stage but is avoided in the higher stages to prevent anybreakdown caused by the well-known avalanche effect.

The third stage 3 is substantially identical to the second stage 2 andcomprises transistors T₄ and T₅, the bases of which are coupled by aninductor L₅, and the collector of transistor T₄ being coupled to thethird bias circuit 6 and to the base of a base current compensationtransistor T₁₃. The collector of transistor T₅ is connected via aninductor L₆ to a positive supply voltage V_(s). At the collector oftransistor T₅ the output signal V_(out) of the power amplifier 100 isproduced, in the embodiment shown via an impedance matching circuit 7.

Although the power amplifier 100 of FIG. 1 is shown to have a double setof converters (41 & 42; 51 & 52; 61 & 62) so to be able to receive twogain control signals corresponding with two distinct modes of operation,this is by no means necessary and in many embodiments only a single setof converters will be provided, that is, only one converter per biascircuit. It is, on the other hand, also possible to provide three ormore converters per bias circuit so as to be able to receive three ormore gain control signals, possible corresponding to three or moredistinct modes of operation.

In FIG. 1, each bias circuit is shown to have a single current mirrorcircuit (40; T₆ & T₇ in bias circuit 4). In the alternative embodimentshown in FIG. 2, however, the first bias circuit 4 comprises two currentmirrors 40 and 40′. Current mirror 40, consisting of transistors T₆ andT₇ and coupled to converter 41 to provide a bias current in response togain control signal V_(c1), is connected as in the first stage 1 of FIG.1, supplying a bias current to the base of transistor T1. Additionalcurrent mirror 40′, consisting of transistor T₆′ and T₇′ and coupledwith converter 42, is arranged to provide a bias voltage, rather than abias current, as in the second stage 2 and the third stage 3 in FIG. 1.To this end, an additional transistor T₁₄ is provided which, togetherwith transistor T₁, constitutes a current mirror circuit for DC signals.As in FIG. 1, a transistor T₁₆ provides a suitable base current fortransistor T₁.

The arrangement of FIG. 2 allows current and voltage biasing to be usedalternatively. In other words, in response to gain control voltagesV_(c1) and V_(c2) a suitable biasing mode can be selected. It will beunderstood that additional converters can be provided to allowadditional gain control signals to be received and to be converted intosuitable bias currents or bias voltages. It can also be envisaged thatthe arrangement of FIG. 2 is used to simultaneously provide a biascurrent and a bias voltage.

Another alternative embodiment of the first bias circuit 4 is shown isFIG. 3, where a compensation transistor T₁₅ is arranged between theconverter 41 and the current mirror 40. This compensation transistor T₁₅serves to compensate for any variations in the current gain factor betaof signal amplifying transistor T₁. The compensation transistor T₁₅ ispreferably matched to transistor T₁ so that both transistors havevirtually identical current gain factors beta. Transistor T₁₅effectively divides the (bias) current in current mirror 40 by beta,while transistor T₁ multiplies this current by beta, thus effectivelycanceling out beta. As a result, the bias current is independent frombeta. It will be understood that this arrangement can be applied in thecircuits of both FIG. 1 and FIG. 2.

In a further advantageous embodiment (not shown), a singlevoltage/current converter supplies bias currents to two or more parallelfirst stages 1, or parallel first signal amplifying transistors T₁, T₁′in a single first stage 1.

It will be understood that the features of the above embodiments may becombined as desired. For example, a first stage could have both a betacompensation transistor and a combined voltage and current bias circuit.

A particularly advantageous embodiment of a voltage/current converter isshown in FIG. 4. The converter of FIG. 4, which may constitute any orall of converters 41, 42, 51, 52, 61 and 62 of FIG. 1, essentiallyconsists of a differential stage circuit comprised of transistors T₂₁and T₂₂, which in the embodiment shown are bipolar NPN-type transistors,the emitters of which are connected via a resistor R₂₁. The base oftransistor T₂₁ receives a control voltage V_(c) via a resistor R₂₂,while transistor T₂₂ receives a reference voltage V_(r1) via a resistorR₂₃. The collector of transistor T₂₂ is connected to a supply voltageV_(s), while the collector of transistor T₂₁ is connected to one of thecurrent mirrors 40, 50, 60 of FIG. 1. Current sources S₁ and S₂ areconnected to the emitters of T₂₁ and T₂₂ respectively. In a preferredembodiment the currents of current sources S₁ and S₂ have substantiallyequal magnitudes. The output current I_(out) is constituted by thecurrent flowing into the collector of T₂₁.

An alternative embodiment of a voltage/current converter according tothe present invention is shown in FIG. 5. Part of this converter isidentical to the one of FIG. 4 and constitutes a first differentialstage circuit with transistors T₂₁ and T₂₂, resistors R₂₁, R₂₂ and R₂₃,and current sources S₁ and S₂ connected as before. A second differentialstage circuit, consisting of transistors T₂₃ and T₂₄, resistors R₂₄ andR₂₅ and current sources S₃ and S₄ is connected in parallel to the firstcircuit. Transistors T₂₂ and T₂₄ receive a reference voltage V_(r1) andV_(r2) via resistors R₂₃ and R₂₅ respectively, while transistors T₂₁ andT₂₃ both receive the control voltage V_(c) via a resistor R₂₂. In thepreferred embodiment, the reference voltages V_(r1) and V_(r2) are notequal, resulting in different “opening points” per circuit, that is,different values of the control voltage V_(c) at which the particularcircuit will start to conduct. The currents I_(out1) flowing into thecollector of transistor T₂₁ and I_(out2) flowing into the collector oftransistor T₂₃ together form output current I_(out).

The circuit of FIG. 5 utilizes the two differential stages to produce anon-linear relationship between the input voltage V_(c) and the outputcurrent I_(out). The inventors have found that this non-linearrelationship is particularly suitable for producing a bias current as inthe circuits of FIGS. 1-3. In addition, the circuit of FIG. 5 isrelatively simple and economical.

The non-linear relationship between the control voltage V_(c) and theoutput current I_(out) in the circuit of FIG. 5 is schematicallydepicted in FIG. 6. Below a certain threshold voltage, the outputcurrent I_(out) will be virtually zero, this area is indicated I in FIG.6. In a second area II, only the first differential stage (transistorsT₂₁ and T₂₂) are conducting and the output current I_(out) (=I_(out1))rises approximately proportionally with the control voltage V_(c). Thenanother threshold voltage is reached and in an area III bothdifferential stages are conducting, resulting in a total output currentI_(out) (=I_(out1)+I_(out2)) which rises more than proportionally withthe control voltage V_(c). It can thus be seen that the converter as awhole exhibits a non-linear behavior which, as the inventors have found,is very suitable for providing bias currents in power amplifiers. Theregions I, II and III, as well as the slope of the curve are welldefined by the resistors. Due to the balanced structure the outputcurrent is temperature and supply voltage independent and virtuallyinsensitive to process spread. In addition, the circuit of FIG. 5 isrelatively simple and economical.

In the circuits described above, in particular those depicted in FIGS.1-3, additional components may be provided in practical embodiments forthe purposes of, for example, filtering or setting the operating pointof the transistors of the various current mirrors. In the circuit ofFIG. 3, for example, two resistors could be provided between the basesof transistors T₆ and T₇, the junction point of the transistors beingconnected to the collector of T₆. A capacitor could be connected betweenthe base of transistor T₇ and the supply for noise suppression purposes.Another capacitor could be connected between the collector of transistorT₇ and ground, and a resistor could be connected between the collectorof T₇ and the first stage 1. It will be understood that such componentsare not essential to the present invention and can be added or omittedas may be required in a specific embodiment.

The power amplifier of the present invention may suitably partitionedinto sections embodied in different technologies. In the embodiment ofFIG. 1, for example, the third stage 3 and possibly the second stage 2can advantageously be implemented in GaAs (gallium arsenide), theremainder of the power amplifier being implemented in Si (silicon), thusexploiting the advantageous high frequency properties of circuitsimplemented in GaAs.

The present invention is based upon the insight that a well-defined biascurrent fed to a signal amplifying transistor allows an amplifier stageto have a well-defined gain. The present invention utilizes the furtherinsight that non-linear bias circuits may produce very desirable overallamplification characteristics.

It is noted that any terms used in this document should not be construedso as to limit the scope of the present invention. In particular, thewords “comprise(s)” and “comprising” are not meant to exclude anyelements not specifically stated. Single (circuit) elements may besubstituted with multiple (circuit) elements or with their equivalents.

Although various aspects of the present invention have been explainedabove with reference to multi-stage power amplifiers, it will beunderstood that the teachings of the present invention are not solimited. Accordingly, providing a suitable bias current into the base ofa signal amplifying transistor in the manners indicated above is alsoadvantageous in, for example, single-stage amplifiers and non-RFamplifiers. Similarly, the “multi-mode” arrangement discussed abovewhich allows multiple distinct bias signals to be supplied to biascircuits in dependence on one or more gain control signals can equallywell be applied to single-stage amplifiers. In addition, this“multi-mode” arrangement may also be utilized independently, that is,without the bias current measures discussed above.

It will therefore be understood by those skilled in the art that thepresent invention is not limited to the embodiments illustrated aboveand that many modifications and additions may be made without departingfrom the scope of the invention as defined in the appending claims.

1. A power amplifier comprising: a first stage including a signalamplification transistor for amplifying an input signal, the signalamplification transistor having a control electrode responsive to a biascurrent, and a first bias circuit including a controlled current sourcefor converting a gain control voltage to the bias current, wherein thebias circuit includes a non-linear voltage/current converter forconverting the gain control voltage to the bias current.
 2. The poweramplifier according to claim 1, wherein the non-linear voltage/currentconverter coupled to a current mirror for providing the bias current tothe control electrode.
 3. The power amplifier according to claim 2,wherein the non-linear voltage/current converter includes at least onedifferential stage coupled to a reference voltage.
 4. A power amplifiercomprising: a first stage for amplifying an input signal, and a firstbias circuit for providing a bias current to the first stage, the firstbias circuit including a controlled current source, and the first biascircuit being arranged for feeding its bias current to a controlelectrode of a signal amplification transistor of the first stage,wherein at least one bias circuit comprises two distinct voltage/currentconverters for converting two distinct gain control voltages.
 5. Thepower amplifier according to claim 1, wherein the first bias circuitfurther includes bias voltage means for providing a bias voltage to thefirst stage.
 6. A power amplifier comprising: a first stage foramplifying an input signal, and a first bias circuit for providing abias current to the first stage, the first bias circuit including acontrolled current source and a voltage/current converter, and the firstbias circuit being arranged for feeding its bias current to a controlelectrode of a signal amplification transistor of the first stage,wherein in the first bias circuit an additional transistor is coupledbetween the voltage/current converter and the controlled current sourceso as to compensate for a DC current gain of the signal amplificationtransistor.
 7. The power amplifier according claim 1, furthercomprising: a second stage for amplifying a signal output by the firststage; a second bias circuit for providing a second stage bias currentto the second stage; a third stage for amplifying a signal output by thesecond stage; and third bias circuit for providing a third stage biascurrent to the third stage.
 8. The power amplifier according to claim 1,wherein the power amplifier is arranged for amplifying high frequencysignals.
 9. A device provided with a power amplifier according to claim1.